lonsta
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Hi, I am considering how to translate a verilog expression to VHDL as :
I write some vhdl code like this :
In verilog, the 'carry' and 'phase_acc' signals refresh the values at every clock, but in VHDL, it seems that carry and phase_acc have to wait for a clock period as there is a pipeline and get the value at the next-next clock edge.
because I don't know how to put two signals together as the signal sinks,e.g. a&b <= c+d is not allowed in VHDL which we can do in verilog using {}.
so, if I want get the carry and phase_acc just next clock, how would I optimise my code, any advice is appreciated...
Code:
{carry, phase_acc} <= (carry ? init_phase : 0) + phase_acc + phase_step;
I write some vhdl code like this :
Code:
----------
phase_step : in std_logic_vector(11 downto 0);
-------something something-------
signal pha_acc : std_logic_vector(11 downto 0);
signal carry : std_logic;
signal pha_tmp : std_logic_vector(12 downto 0);
---something -------
clock here---
if (carry = '1') then
pha_tmp <= ('0'&init_phase) + ('0'&phase_acc) + ('0'&phase_step);
carry <= pha_tmp(12);
phase_acc <= pha_tmp(11 downto 0);
else
pha_tmp <=('0'&phase_acc) + ('0'&phase_step);
carry <= pha_tmp(12);
phase_acc <= pha_tmp(11 downto 0);
end if;
In verilog, the 'carry' and 'phase_acc' signals refresh the values at every clock, but in VHDL, it seems that carry and phase_acc have to wait for a clock period as there is a pipeline and get the value at the next-next clock edge.
because I don't know how to put two signals together as the signal sinks,e.g. a&b <= c+d is not allowed in VHDL which we can do in verilog using {}.
so, if I want get the carry and phase_acc just next clock, how would I optimise my code, any advice is appreciated...