verifying top level schematics

[svensl]

Hello all,

this might be a trivial question but I was wondering how people go about checking whether there are no unintended connections in large designs.
Obviously, a "check and save" will reveal unconnected lines and also whether the signal lines have the same number of bits as the blocks their being routed to.

However, a "check and save" won't flag if I am using the same bus-bit for two blocks, ie. have signal<3> used on two different blocks by accident. Is there a way of checking whether each bit has only one connection?

Any tips on how people go about checking their top level schematic are appreciated.

Thanks,

 

[carl_chao]

The best way is to do final toplevel sims, vary the singals and check or compare the results with your say, behavior model, using the same setup but switching the model card. Usually you do this with Cadence's AMS or Mentor's AdvanceMS.

 

[svensl]

Thanks,

most of the signals I did verify using mixed mode simulations as each block has a verilogams view. However, this is more to check the interaction with the digital (verilog) block which controls the entire chip. ATB (analog test bus) lines and bias lines are not checked by the mixed sims, hence I was wondering whether there is a feature in cadence which flags a warning when they're hooked up wrong. I could always trace all lines by hand or in the netlist, but hey, there might be a more atomated way.


cheers,