Verification techniques for FPGA prototyping.

[ghegde]

Hello,
I am in the phase of designing and implementing a digital circuit for a FPGA.I wonder how a digital circuit logic(described in HDL) is verified before synthesizing to a FPGA.I used to write test bench for simple digital circuit before but the design at hand is now complex and writing test bench doesn't look like a wise approach.I have heard of verification techniques like OVM/UVM, but not sure whether they are used for verification of logic intended for FPGA.Are there any other technique that I can use?or OVM/UVM is still the best option?

Any help is greatly appreciated.

Thanks,
Ganesh

 

[TrickyDicky]

You need to design a testbench that covers as many cases as possible. They are still referred to as testbenches, even when using UVM.
UVM is just a system verilog library of common module behaviour and checkers. So its not a method in itself - a poor testbench using UVM is still a port testbench.
You need to think about your test plan? whars the input? do you need constrained random testing? Asserting based verification?
All of the techniques can be done in VHDL or System Verilog. But SV has alot more available already setup for you - like UVM.

So - what are you trying to do?

 

[ghegde]

Thanks TrickyDicky for the reply.
The actual Design Under Test(DUT) will be a router for NoC(Network on Chip). The design is not yet ready but I am just thinking about the verification techniques in advance.

Thanks
Ganesh

 

[TrickyDicky]

This is a recommended book about verification:
https://www.amazon.co.uk/Writing-Testbenches-Functional-Verification-Models/dp/1402074018