Verification Plan for FIFO

[pralach]

Hi
I have come across a interview question on FIFO, question is, how to write top level verification plan for asynchronous FIFO and what are test-case do you write to verify the DUT ? I would appreciate help on the same.

Regards
Pralach

 

[sree205]

some aspects which i can think about.

1. see if full and empty signals get asserted properly
2. try a read when its empty
3. try a write when its full
4. write and a read at the same time if possible

Added after 42 seconds:

check this page as well

 

[pralach]

Thanks for quick response.I have one more questions.

1.My Understanding is that , the test-cases mentioned are trying to verify the depth of the FIFO and full/empty conditions.I would like to know how to verify frequency of write pointer and rd_pointer, to check whether write and read are happening on expected frequency of spec , I mean verifying the write and read frequencies ?

2.What is the significance of synchronous FIFO ( I mean if both write and read will happen on the same frequency as per definition of synchronous FIFO, why do we need the same as both writing and reading interface runs at same frequency ?

 

[nsingh95]

Thanks for quick response.I have one more questions.

1.My Understanding is that , the test-cases mentioned are trying to verify the depth of the FIFO and full/empty conditions.I would like to know how to verify frequency of write pointer and rd_pointer, to check whether write and read are happening on expected frequency of spec , I mean verifying the write and read frequencies ?

2.What is the significance of synchronous FIFO ( I mean if both write and read will happen on the same frequency as per definition of synchronous FIFO, why do we need the same as both writing and reading interface runs at same frequency ?

##################################################
Hi,
This all depends on the specification.You can operate FIFO with different conditions.May be your project requires simultaneous read/write operations.
See , to verify your read/write operations, you should have the clear picture of specification.
Some testplan can be.
1 .Write to n locations , read it back.
2 . write /read at the same time.
3. 1 & 2 with random data and address.
4. Fifo depth, fifo empty.
5 . What will happen if during write/read operation some interrupt occur in master device. And so on.

 

[asicengineer1]

To answer ur 2nd question, think of this scenario.

writing into the FIFO is being done with a burst of 8 and reading is done with bursts of 4 with a delay between 2 reads, which is not a multiple of the clock frequency you are using. In such a scenario, synchronous fifo will be used.