anuradha.verma
Junior Member level 3
Hello
Can anyone tell me how i can verify the layout(output) of IC compiler
Can anyone tell me how i can verify the layout(output) of IC compiler
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hi anu..
To check Layout u have check LVS (Layout Versus Schematic) It will check compare the connections with schematic....another one is u have to check DRC(DesignRuleCheck) It wll check spacing error between the metal layers etc... I think these details u may know... What do you want to check ?? tell it clearly..
hello,
i want whether the layout which i got is correct or not.Is herculus is the tool which should be used for this purpose.
hi.......
Tools like calibre,hercules,Assura using these we can check the layout...It depends upon the vendor 's rule deck file..They will mention the tool to be used for certain rule file..