verification of fifo status....

[nitish tomar]

hw to check the following conditions in fifo
1. full
2. full-1
3. empty
4. empty-1
pls reply ................

 

[jpvSoccer]

How is your FIFO designed? RTL, gates, IP-block

What are the inputs and outputs of the FIFO?

 

[nitish tomar]

How is your FIFO designed? RTL, gates, IP-block

What are the inputs and outputs of the FIFO?

my fifo is generic, it is connected to a generic cpu. having comparaters, counters and a register block connecting it to cpu....
so, can i test these condition by push and pop of data in my test cases.??

 

[jpvSoccer]

Hi, FIFO's often have outputs that indicate FULL/EMPTY.

If yours does not, you probably need to monitor internal signals, pull them out of the block, or create them in RTL.