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verification in vhdl/verilog

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lucky_2

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hello,

Can any body provide me the study material regarding the verification in vhdl/verilog

waiting for response
 

vvvvv

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try search in EDA Ebook upload download forum for
verification, there a lot of free points book for download
 

the_penetrator

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Well,

the most organized attempt to verification constructs in pure VHDL/Verilog is the OVL library:
https://www.accellera.org

However, it seems that accellera has chosen not to promote the VHDL implementation but only the SystemVerilog OVL. I believe it is not expected to see any revision on the VHDL OVL implementation (dates back to 2003).

cheers

the_penetrator©
 

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