verification environment in VHDL and verilog

[sougata_vlsi13]

can anyone please share any views what exactly mean by verification environment.Generally we go for test benches in VHDL and verilog..is there any other verification environment(not about system verilog..other than that).Means there is a design and i have to verify that like that whether it s correct or not...or from where can i able to know more about these things...please tell

 

[achaleus]

you can say verifying your design with already done software or hardware counterpart. eg: fft output you can verify with xilinx ip core fft or with matlab fft operator.. or fft code written in c language.. etc

 

[TrickyDicky]

Verication environment usually refers to your suite of tests and testbenches.

 

[dave_59]

Your testbench is just one component of your verification environment. Your testbench is the architecture around your Device Under Test (DUT) that stimulates the inputs and monitors the outputs of your DUT. Most likely your testbench also includes checkers or scoreboards that compare actual to expected outputs. Your testbench can be written in a number of languages depending the application that best suits the algorithms involved. The verification environment encompasses every thing else you need to configure the testbench to run individual tests. That could be other tools that generate stimulus data (MatLab) and tools to process output (PERL). Another part of your verification environment is controlling how you run a suite of tests (regression run management) and measure progress (functional coverage analysis). This is all to answer the big question "Are we done yet?"

 

[sougata_vlsi13]

Thank you everyone for your reply