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Verification concept, Environment and testbench

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vinhphuong

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Verification concept

Can anyone explain me the difference between:
- Environment and testbench
- Verification strategy and verification plan
Thanks
 

semiconductorman

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Re: Verification concept

- Environment and testbench
testbench usally refers to a simple wrapper written over the RTL design to check the functionality.
Enivronment - with the designs getting complex and running into millions of gates it is not possible to have a simplicistic testbech so there are verification components developed like generators, monitors, checkers etc. all these components together form the environment.
I suggest you read "writing testbenches" by Janik B. It explains all these details very well.

Verification strategy and verification plan
Strategy is how you plan to tackle the task of verifying your design for example directed test cases, random testing, combination of the 2 etc.

Verification plan is a record of what needs to be tested. But I must warn you these are terms that are used interchangingly and might mean different things in different companies :)
 

    vinhphuong

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