xxcxy
Newbie level 2
$fs_ verilog
Hi!
I have a Problem with my fault simulation.
First I created the schematic with the schematic-composer tool.
Next I did the Functional Simulation with Verilog-XL which works well. (I`m workin with the Verilog-XL Integration Control tool and a stimulus-file(test.verilog)).
Then I created a stimulus file called test.verifault (under a new run-directory), but when I`m compiling this file with the Integration tool I get for every Verifault-XL task in the stimulus file this message:
Skipping foreign Verifault task $fs_........
Is it possible that this has something to do with my .simrc-file
Thanks in advance for your help!
Hi!
I have a Problem with my fault simulation.
First I created the schematic with the schematic-composer tool.
Next I did the Functional Simulation with Verilog-XL which works well. (I`m workin with the Verilog-XL Integration Control tool and a stimulus-file(test.verilog)).
Then I created a stimulus file called test.verifault (under a new run-directory), but when I`m compiling this file with the Integration tool I get for every Verifault-XL task in the stimulus file this message:
Skipping foreign Verifault task $fs_........
Is it possible that this has something to do with my .simrc-file
Thanks in advance for your help!