J0nnnn
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Hi all,
I'm trying to simulate a mixed design in Verdi, but I'm having a problem. I'm using the command 'verdi -f flist -vhdl' where flist is a list of files (both verilog and vhdl). When I have the -vhdl option it treats all files as vhdl, so the verilog ones give errors. Without the -vhdl option, I get errors for the vhdl.
I'm compiling everything in VCS if that makes any difference.
I'm very new to digital design, so I may be missing something very simple.
Thanks
I'm trying to simulate a mixed design in Verdi, but I'm having a problem. I'm using the command 'verdi -f flist -vhdl' where flist is a list of files (both verilog and vhdl). When I have the -vhdl option it treats all files as vhdl, so the verilog ones give errors. Without the -vhdl option, I get errors for the vhdl.
I'm compiling everything in VCS if that makes any difference.
I'm very new to digital design, so I may be missing something very simple.
Thanks