abhinav1088
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Hi all,
I am compiling a .sv file and I am getting the following error -
syntax error - illegal use of SystemVerilog keyword 'wildcard' at current location.
The code snippet is -
a1_covergrp : cross mode_1, mode_2, mode_3 iff (---) {
wildcard ignore_bins b1 = binsof (mode_3) intersect {4'b0???};
}
Any help will be useful.
I am compiling a .sv file and I am getting the following error -
syntax error - illegal use of SystemVerilog keyword 'wildcard' at current location.
The code snippet is -
a1_covergrp : cross mode_1, mode_2, mode_3 iff (---) {
wildcard ignore_bins b1 = binsof (mode_3) intersect {4'b0???};
}
Any help will be useful.
