vector waveform for AND gate

[vead]

hello everybody
I am trying to make vector waveform for AND gate using quartus
I have uploaded file

please check that waveform file and tell why logic level is not correct ?

 

[j_andr]

- check if the file you think is the sim input is the same as in Settings->Simulation Settings-> Simulation input
- change 'X' in the inputs to '1' or '0' in the input vwf file
- cyclone3 is not very fast device, make input levels stable longer than 10ns

j.