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vdsat for current mirror in 0.25um process

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QwErTzY

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Hi, I have design a current mirror in 0.25um 5V process.
At typical case, the vdsat is 0.25V and vds is 0.5V
At one worst case corner, my vdsat is 0.19V and vds is 0.21V
At another worst case corner, my vdsat is 0.15V vds is 0.25V

The current mirror is a cascode design and able vdd varies from 3V-5V.

Is this design risky? Will it cause the current mirror to go into linear region or is there any potential risk? What are the potential problems that i need to take note?
 

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