Vctrl of VCO in PLL, so strange!

[lifusu]

hi guys!
i design a pll (verilogA), 12MHz input , C2=400p, C1=40p, R2=3.3k，bandwidth＝600k，Kvco＝600MHz/v，Icp＝20uA，when locked , the wave of Vctrl is as follows, why the Vctrl like this? i don't think it is ripple.
But when i delete divider, this condition will not occur, but the divider is ideal , why?
thx in advance!

 

[lifusu]

another Q.
when i set the Vctrl 0v initially, the wave is as Fig.1;
when i set the Vctrl 0.5v initially, the wave is as Fig2.

 

[keith1200rs]

I don't know the software you are using but I would suggest you adjust the simulator settings - the erratic results look like timestep problems. Reduce the value of the maximum timestep.

Keith

 

[varunkant2k]

are you using any initial condition for your rc filter. try to use some 0.5Vlts to your filter as initial voltage.
Show us the AC response of your model.

 

[lifusu]

I am using spectre and just as you said, it is really timestep problems! Thank U so much!
and also thank varunkant2k!