faizalism
Member level 4
Hi,
I have problem compile verilog files that contained 'var' . Log file shows :
Error-[SE] Syntax error
Following verilog source has syntax error :
"tryitout.sv", 27: token is 'var'
input var real n_out, p_out;
^
System verilog keyword 'var' is not expected to be used in this context.
Here are my switches that I am using: -sverilog -timescale=1ps/1ps -debug_all
Any input guys?
I have problem compile verilog files that contained 'var' . Log file shows :
Error-[SE] Syntax error
Following verilog source has syntax error :
"tryitout.sv", 27: token is 'var'
input var real n_out, p_out;
^
System verilog keyword 'var' is not expected to be used in this context.
Here are my switches that I am using: -sverilog -timescale=1ps/1ps -debug_all
Any input guys?