VCS error as simulation is not progressing

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er_sonal

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verilog

Can anyone tell me the reason if my simulation does not progress,
my tool is VCS. I tried to change timscale but then also my simulation is not
progressing ,i.e.,( suppose i am designing a counter to count 300*10*6 counts,
but simulation gets stopped in between ) .

Thanks and Regards
 

Re: verilog

You can specify your simulation time $finish, in your test bench.
specify it as $finish 9000; Which would run for 9000 counts...
 

verilog

you should check there are $finish and $stop in your design or not
 

verilog

actually, i believe it should be #9000 $finish.
 

Re: verilog

Can you post ur code here so that we can try reproduce the problem at our end!!!
 

verilog

did u make sure that the same timescale is used in ur testbench and ur RTL file ?
 

Re: verilog

Ya timescale was there in my code.
It was 1ns/1ps
 

verilog

probably coz, u want to count 18000 times and ur simulation time is a lot less than that. i.e. half of ur total count.
 

Re: verilog

Do you mean it hangs or stops and comes out? If it hangs, may be you have a combinatiorial loop? Try debugging through VCS's UCLi command line.

Ajeetha, CVC
www.noveldv.com
New Book: A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
https://www.systemverilog.us/
 

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