mydreamhouse
Advanced Member level 4
i meet a funny problem in my vco layout
the process is smic018rf,and eda software is cadence.
when i extract the post netlist from layout(mentor calibre),i found that for the same size NMOS RF transistor,their gate poly's parastical risistance is not the same. one is about 300, and the other is 1K, what's the problem of layout
the process is smic018rf,and eda software is cadence.
when i extract the post netlist from layout(mentor calibre),i found that for the same size NMOS RF transistor,their gate poly's parastical risistance is not the same. one is about 300, and the other is 1K, what's the problem of layout