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VCO layout problem with different poly's parasitical resistance values

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mydreamhouse

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i meet a funny problem in my vco layout
the process is smic018rf,and eda software is cadence.
when i extract the post netlist from layout(mentor calibre),i found that for the same size NMOS RF transistor,their gate poly's parastical risistance is not the same. one is about 300, and the other is 1K, what's the problem of layout
 

safwatonline

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vco layout help

it is an LVS error , try to solve the discripancies
 

mydreamhouse

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Re: vco layout help

i have check out the LVS before PEX and LVS is no problem
 

mydreamhouse

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Re: vco layout help

the schematic is in workstation,
the simulation is no problem before layout
 

elbadry

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Re: vco layout help

The poly gate resistance depends on the way you contact the poly gate.

If you are contacting from a single side you get 4 times the resistance that you can get if you contact the gate from both ends.

Not sure if this is your problem though
 

mydreamhouse

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Re: vco layout help

RF MOS instance is designed by SMIC, so, poly contact is no problem
i found that if i insert a small in Gate branch , and the resistance of the Gate become normal. but why?
 

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