Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

VCDL requirement in DLL

Status
Not open for further replies.
G

gggould

Member level 3
Joined
Apr 10, 2004
Messages
63
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
532
Hi,
Does anyone know what is the requirement for the VCDL delay time to avoid false locking?
My understanding is Tref>Tvcdl_min>0.5*Tref, and Tref<Tvcdl_max<1.5*Tref.
I can understand both later parts, but why does Tref>Tvcdl_min and Tref<Tvcdl_max criteria come from?

Thanks.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top