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Various questions about Clock Tree Synthesis

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snr_vlsi

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Hi

Let’s say there enough routing resources available, timing is fine, can you increase clock buffers in clock network? If so will there be any impact on other parameters?

How do you optimize skew/insertion delays in CTS?

What are differences in clock constraints from pre CTS (Clock Tree Synthesis) to post CTS (Clock Tree Synthesis)?

What constraints you add in CTS (Clock Tree Synthesis) for clock gates?

What do clock constraints file contain?

How to analyze clock tree reports?

How do you minimize clock skew/ balance clock tree

thx

snr_vlsi
 

MarcS

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Re: cts

Let’s say there enough routing resources available, timing is fine, can you increase clock buffers in clock network? If so will there be any impact on other parameters?
Yes, you can add buffers to your clock network, but why? If your timing is OK, why do you want to add buffers to your design? If you just want to increase the insertion delay of the clock by adding buffers just below the root, you can do that if you want (but why?). If you start putting buffers anywhere else in the clock network you risk increasing the skew and/or increasing the insertion delay. And, of course, more or bigger buffers means more dynamic power consumption.

How do you optimize skew/insertion delays in CTS?
Skew and insertion delay are parameters that pull against each other. If you want to decrease your skew you have to add more buffers which increases your insertion delay. The way CTS tools work is that first the flip-flops are clustered, then a buffer tree is built that distributes the clock signal with an acceptable slew, and finally buffers are added to balance all the endpoints in the tree. The details of the techniques are complex and typically trade secrets.

What are differences in clock constraints from pre CTS (Clock Tree Synthesis) to post CTS (Clock Tree Synthesis)
Pre-CTS constraints are called clock network latency and clock uncertainty. After the clock is built, these are measured as insertion delay and skew.

What constraints you add in CTS (Clock Tree Synthesis) for clock gates?
Clock gates, like any other sequential element, have a setup and hold check on their enable input. In other words, a clock gate adds another timing path (the clock gate enable path) that must be satisfied.

What do clock constraints file contain?
Clock constraints consist of some of the following:
(a) clock definitions with a waveform, a source point, and a network latency and skew
(b) source latency definitions for clocks
(c) generated clock definitions (and virtual clock definitions)
(d) input delays and output delays
(e) balancing constraints (only in some formats - not SDC)
(f) stop pins (only in some formats - not SDC)
(g) timing exceptions such as multicycle paths and false paths (not strictly clock info)
(h) guidance on desired tree structure (number of levels, gates to use, ...)

How to analyze clock tree reports?
Check if the insertion delay targets and skew targets have been met for all clocks.

How do you minimize clock skew/ balance clock tree
It is a difficult task almost always done by an automatic tool. You insert the correct types and number of buffers at the correct locations to balance the tree. Some older methodologies rely on H-trees or clock meshes, but these do not work well with modern technologies.

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