shaiko
Advanced Member level 5
My application involves a battery powered FPGA that's idle most of the time and starts doing "hard work" only when given an external command over a communication channel. I want to reduce the power conssumption. If I could, I'd shut down the FPGA's clock altogether, but because I have to keep the communication channel alive - I can't just shutdown the clock.
I had an idea:
the global clock of the FPGA will be driven by a voltage controlled oscillator. This oscillator will be controlled by the FPGA - thus enabling it to boost its own speed when woken up.
What do you think?
I had an idea:
the global clock of the FPGA will be driven by a voltage controlled oscillator. This oscillator will be controlled by the FPGA - thus enabling it to boost its own speed when woken up.
What do you think?