Variable speed clock for an FPGA

[shaiko]

My application involves a battery powered FPGA that's idle most of the time and starts doing "hard work" only when given an external command over a communication channel. I want to reduce the power conssumption. If I could, I'd shut down the FPGA's clock altogether, but because I have to keep the communication channel alive - I can't just shutdown the clock.

I had an idea:
the global clock of the FPGA will be driven by a voltage controlled oscillator. This oscillator will be controlled by the FPGA - thus enabling it to boost its own speed when woken up.
What do you think?

 

[ads_ee]

You could do that, but you'll likely have issues with any internal PLLs in the FPGA as they usually require knowledge of the period of the input clock.

I suggest you use the internal PLL of the FPGA and use the slowest clock that is supported (probably something around 20MHz) and generate a 4x-5x output that you can shutdown via the dynamic reconfiguration of the FPGA that you are using. Both Xilinx and Altera support the dynamic reconfiguration of PLL settings via a configuration port on their PLLs. I know Xilinx has some stipulations on what can be changed on the fly using that port.

If you're using an FPGA with no PLL then your proposed method is probably the only way you'll be able to do what your suggesting.

You could also use a SPI interface for control and actually use the SPI clock, but you'll have to design a SPI slave inteface that won't be synchronous to any other clock in the design. It's much easier to use a constant clock output of a PLL and sample the SPI signals.

 

[permute]

altera and xilinx both have clock muxing features. you can have a slow clock and a fast clock and mux between the two.

If needed, you could even shut down any PLL used to get the fast clock, assuming it can relock in time to do processing.