variable question in VHDL

[Digit0001]

Hi
Can someone tell me if this is true, Variables declared inside a clocked process are treated as signals for the purpose of synthesis.

P.S

 

[asjohnas]

Variable this is definition your task like combinatorial logic. For correct synthesis of it you need connect this combinatorial logic to triger.

 

[TrickyDicky]

The answer is that you're kind of correct.
Variables are converted to logic just like any signal, but the position of the variable in the code has an effect whereas a changing the position of a signal would have no effect. Because variables are updated immediatly they can be used to create combinatorial logic inside a clocked process.

an example. The first two processes are identical.

process
begin
  if rising_edge(clk) then
    a <= input;
    b <= a;
    c <= b;
    output <= c;
  end if;
end process;

process
begin
  if rising_edge(clk) then
    output <= c;
    c <= b;
    b <= a;
    a <= input;
  end if;
end process;

Both of these processes produce exactly the same logic - a shift register that has a delay of 4 clock cycles.

now the same codes using variables:

process
begin
  if rising_edge(clk) then
    a := input;
    b := a;
    c := b;
    output <= c;
  end if;
end process;

In this case, because variables are updated immediatly, then the output only has a single register between the input and output.

process
begin
  if rising_edge(clk) then
    output <= c;
    c := b;
    b := a;
    a := input;
  end if;
end process;

In this process, the synthis will produce the same logic as if a,b and c were signals, because you are using the variable before it is updated with new value - hence it places a register (so output is a 4 clock cycle delayed version of input).

 

[Digit0001]

ok i understand now

---------- Post added at 10:35 ---------- Previous post was at 10:31 ----------

however in general cases would this happen regularly? I assume most people when designing would not want a code to wait four clock cycles to update a signal.

 

[TrickyDicky]

This is a simple example, showing the behaviours of signals and variables. You may want a shift register of N delay to keep control signals aligned with a data pipeline. So your question doesnt make a lot of sense, because it all depends on your design.

As a general rule - unless you understand what you're doing, use signals. Variables used wrongly can cause problems. You probably wont go wrong with signals.