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Variable input and Constant output(Sepic)

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Here are the gate and drain waveforms
 

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  • Drain Waveform_without Load.png
    Drain Waveform_without Load.png
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  • Gate Pulses_without Load.png
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Very likely the chips limits current on the peak source current (=drain current).

If you design your converter for 3A, and you have a peak peak ripple of 1.5A, the peak current through the mosfet will be 3.75A, (check this with your simulations).

Check the datasheet regarding the protection schemes. You may need to change the source resistor. I hope the source resistor is very close to the chip to avoid voltage spikes because of inductance.

Regarding the resistors. You are right. A 24 Ohms resistor draws 1 Ampere from 24V. The dissipation will be 24V*1A = 24 W. Gradually increasing the load (that is adding more resistors in parallel) will tell you how the circuit will react to steady increasing overcurrent. You may check waveforms for irregularities (for example due to loop instabillity). Try this first before real doing short circuit tests.

Repeated short circuit testing may destroy the output capacitors as standard electrolytic capacitors aren't designed for fast discharge (as used in photo flash units).

---------- Post added at 15:19 ---------- Previous post was at 15:11 ----------

Very strange waveforms,

Can you zoom, because there seems a lot of ringing (HF decaying oscillation) present? I am sure, these results do not match your simulated waveforms. This may be because of diode commutation and/or layout.
 

Hello ,

Here am attaching waveforms of Drain & Gate at No-Load Condition. These waveforms are from LT Spice. Kindly go through it. I hope the same waveforms am getting even on PCB also. Give me sometime,i will post those.
 

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  • Drain And Gate Pulses without load in Simulation.JPG
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Here is the Gate Drain waveforms from CRO. I will zoom it and i will send in next post.
 

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  • Gate and Drain Wave forms from CRO_No Load.png
    Gate and Drain Wave forms from CRO_No Load.png
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Zoomed waveform. Kindly suggest me what to do now??
 

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  • Zoomed Wave form of Drain & Gate Waveform.png
    Zoomed Wave form of Drain & Gate Waveform.png
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Hello,

You have too much ringing at about 1.5 MHz (according to your simulation), so it is good to add a snubber network between drain and source. A snubber network can be a RC series circuit.

Try to search for snubber network dimensioning. This will give you info on how to dimension RC snubbers. Add the components in your simulation and see the effect.
 

Here is the Waveform of Drain and Gate With Load Connected. Now suggest me how to Stop Voltage drop once we connect the Load.
 

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  • Drain and Gate pulses with Load Connected.png
    Drain and Gate pulses with Load Connected.png
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Thanks WimRFP,
So if i add snubber circuit will there any improvement in my output??
 

Here is the Waveform of Drain and Gate With Load Connected. Now suggest me how to Stop Voltage drop once we connect the Load.
This is the only useful waveform you posted. The most concerning thing is that you get one wide gate pulse, then three extremely narrow pulses. I have personally seen this behavior before in current mode converters, and it is often due to overshoot on the current sense signal (often due to poor layout or large FET capacitance). This can be addressed by adding a filter to the current sense signal (see figure 5 of the LT3758 datasheet). There are other methods as well (increasing ripple current helps, and adding gate resistance may solve it too), but adding the filter is the easiest thing.
 

This waveform doesn't look bad, except for the spikes. The drain voltage remains low during on-time. As suggested before:

- Check waveforms and voltage with increasing load current and compare with simulation.
- Study the safety features of the chip, check the dimensioning of the source current limiting resistor.
- Check the ripple voltage at the output (is it what you expect)?
- search on diode cummutation and snubbers as suggested. The snubber you need when the circuit goes into discontinuous mode.

This may require some time, but this is part of the development process.

Regarding the current sense issue. The fet will turn on when in discontinuous mode (as the drain voltage drops after a negative spike). Maybe the current sense circuitry triggers on the reverse recovery current of the diode. I agree with mtwieg to slow down the fet by adding some gate resistance and input filtering for the current sense input of the chip.
 
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Hello mtwieg & WimRFP,

I have included the RC filter circuit at sense pin. Now my voltage just incresed to 8.3V. I have used 25 Ohms and 10nf Capacitor. Can i increase the resistor furher??

Regards,
Samson

---------- Post added at 15:48 ---------- Previous post was at 15:08 ----------

I hope we need to decrease the resistance value...is it??
 

Can you post waveforms of the SENSE and Vc pins, captured simultaneously under load?
 

Ok. If possible have the timescale such that you can see a few switching cycles (like 100us total).
 

Dear mtwieg,

Here is the waveforms of VC & Sense pins under load connected.
 

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  • Sense waveform under load.png
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  • VC Pin Waveform under Load connected.png
    VC Pin Waveform under Load connected.png
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Dear Mtwieg & WimRFP,

One more thing i have observed is, When i connected resistors (10W,22 Ohm) & (5W,22 Ohm ) in series as LOAD, the output voltage gradually decreasing like 22V,16V like that. Kindly tell me how to rectify this problem.

Regards,
Samson

---------- Post added at 13:34 ---------- Previous post was at 13:25 ----------

The voltage is getting drop to till 14V. later it is stable. So at load am getting 14V and current 270mA.
 

Hi,

This is the latest Waveform of drain & gate Pulses with load connected. Kindly go through this. Here am getting the frequency as 36KHZ. But,this design was calculated for 200KHZ. I dnt know why this difference in frequency occurs. How to improve my frequency??

I hope will that voltage drop is due to frequency variation?? Correct me if am wrong.

Thanks in advance.
 

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  • Drain and Gate waveforms with Load Connected1.png
    Drain and Gate waveforms with Load Connected1.png
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Kindly check the drain pulse also. It coming down to zero for very small times somewhere even gate pulse is zero.

---------- Post added at 18:28 ---------- Previous post was at 17:32 ----------

At no load am getting 200KHZ. once i connect load my frequency is getting reduced. I hope this is due to output voltage got dropped.

Kindly assist me as early as possible.
 

Dear mtwieg,

Here is the waveforms of VC & Sense pins under load connected.
It's really hard to see what's going on here... you need to actually zoom in on the signal (both in X and Y) so we can see its shape. And again, it's important to see the two signals simultaneously on the same screen.

Hi,

This is the latest Waveform of drain & gate Pulses with load connected. Kindly go through this. Here am getting the frequency as 36KHZ. But,this design was calculated for 200KHZ. I dnt know why this difference in frequency occurs. How to improve my frequency??

I hope will that voltage drop is due to frequency variation?? Correct me if am wrong.

Thanks in advance.
It looks like in this waveform your scope sampling rate is extremely low, probably because you acquired a very wide window of data and then zoomed in on a very small portion of it. Don't do that.

It still looks like the waveforms are skipping pulses for some reason. Hard to tell. I doubt the actual switching frequency of the converter is dropping (the oscillator frequency isn't changing), but it is skipping most pulses, making it appear to be running slower.
 

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