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Variable Clock Booth Multiplier

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keyboardcowboy

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I have implemented a booth multiplier, and now I want to convert it to a variable cycle (Variable latency) multiplier such that the number of cycles taken to produce an output depends upon the type of input (perform multiple bit shifts to skip over runs of 1s or 0s etc) How can I do this?
 

keyboardcowboy

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ok I have figured out a bit on how to do this, but still need some help..booth multiplier only generates a partial product if there is a 10 or a 01 so if there are multiple groups of 00 I can skip that (don't have to waste a cycle on that) now i need to figure out a way to scan the multiplier for position of 00 so that they can be skipped
 

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So do you also skip over 11 too? If so that is an XNOR of a pair of bits.

You could scan (scan === slow) pairs of input bits, or do the operation in parallel and get a parallel output that translates into a skip shift control word. The skip shift control has a 1 for every pair of bits that is 00 or 11, so you shift 2-bits over for the input (and 1-bit of the skip shift control word). This could just become part of the scan and shift operation in your first post.

Hmmm, this still seems too slow. You might want to use the skip shift control word and translate a string of 1's into a mux control to select the number of shifts to perform in a single clock cycle.

e.g. (using 16-bit input)
Code:
16-bit word: 1001110100001110
bit pairs:   10 01 11 01 00 00 11 10 
sscw:         0  0  1  0  1  1  1  0

when sscw == 0 shift
when sscw == 1 weighted shift

compute something like:
shift_ctl = sscw[0] + &sscw[1:0] + &sscw[2:0] .... etc

sscw = 00101110
then shift_ctl = 0 (i.e. normal shift)

sscw = .0010111
then shift_ctl = 1+1+1 = 3 (i.e. shift by 3)

...this shift is done in one clock cycle using the shift count
as the control to a multiplexer.

sscw = ....0010
etc...
Maybe that will help stir up the ol' brain cells.
 

keyboardcowboy

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Thanks for the response, here is my code for the booth multiplier. I am not sure how to proceed to implement what you have mentioned

Code:
module Booth_Multiplier (
    input   Rst,                    
    input   Clk,                    

    input   Ld,                     
    input   [31:0] M,      
    input   [31:0] R,      
    output  reg Valid,              
    output  reg [(64 - 1):0] P   
);


reg     [32:0] A;      
reg     [   32:0] Cntr;   
reg     [32:0] S;      

reg     [(64 + 1):0] Prod,Prod2;   



always @(*)
begin
    case(Prod[1:0])
        2'b01   : S = Prod[(64 + 1):(32 + 1)] + A;
        2'b10   : S = Prod[(64 + 1):(32 + 1)] - A;
        default : begin
        S = Prod[(64 + 1):(32 + 1)];
        end
    endcase
end

always @(posedge Clk)
begin

    if(Rst) begin
        A <= #1 0;
        skip <= #1 0;
        Prod <= #1 0;
        P <= #1 0;
        Valid <= #1 0;
        Cntr <= #1 0;
      end
    else if(Ld) begin
        A <= #1 {M[31], M};
        Prod <= #1 {R, 1'b0};
        Cntr <= #1 32;
      end  
    else if(Cntr > 1) begin
    Cntr <= #1 (Cntr - 1);
    Prod <= #1 {S[32], S, Prod[32:1]};

     end  
    else if(Cntr == 1) begin 
    P <= #1 {S[32], S, Prod[32:2]};
    Valid <= #1 (Cntr == 1);
      end
end


endmodule
 

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