Variable bit widths in structural verilog.

[verilog_noob]

Hi,
For an assignment I have to build a variable bit width ALU. I have built all of the modules (adding, subtracting, and, or, xor, etc...) but have built them all hardcoded to 32 bits.

for example:
my 32bit xor-er

`define D 0
module xor32(
	output [31:0] C,
	input [31:0] A,
	input [31:0] B
    );
//xor all the bits
xor_gate #`D xor0 (C[0], A[0], B[0]);
xor_gate #`D xor1 (C[1], A[1], B[1]);
xor_gate #`D xor2 (C[2], A[2], B[2]);
xor_gate #`D xor3 (C[3], A[3], B[3]);
xor_gate #`D xor4 (C[4], A[4], B[4]);
xor_gate #`D xor5 (C[5], A[5], B[5]);
xor_gate #`D xor6 (C[6], A[6], B[6]);
xor_gate #`D xor7 (C[7], A[7], B[7]);
xor_gate #`D xor8 (C[8], A[8], B[8]);
xor_gate #`D xor9 (C[9], A[9], B[9]);
xor_gate #`D xor10 (C[10], A[10], B[10]);
xor_gate #`D xor11 (C[11], A[11], B[11]);
xor_gate #`D xor12 (C[12], A[12], B[12]);
xor_gate #`D xor13 (C[13], A[13], B[13]);
xor_gate #`D xor14 (C[14], A[14], B[14]);
xor_gate #`D xor15 (C[15], A[15], B[15]);
xor_gate #`D xor16 (C[16], A[16], B[16]);
xor_gate #`D xor17 (C[17], A[17], B[17]);
xor_gate #`D xor18 (C[18], A[18], B[18]);
xor_gate #`D xor19 (C[19], A[19], B[19]);
xor_gate #`D xor20 (C[20], A[20], B[20]);
xor_gate #`D xor21 (C[21], A[21], B[21]);
xor_gate #`D xor22 (C[22], A[22], B[22]);
xor_gate #`D xor23 (C[23], A[23], B[23]);
xor_gate #`D xor24 (C[24], A[24], B[24]);
xor_gate #`D xor25 (C[25], A[25], B[25]);
xor_gate #`D xor26 (C[26], A[26], B[26]);
xor_gate #`D xor27 (C[27], A[27], B[27]);
xor_gate #`D xor28 (C[28], A[28], B[28]);
xor_gate #`D xor29 (C[29], A[29], B[29]);
xor_gate #`D xor30 (C[30], A[30], B[30]);
xor_gate #`D xor31 (C[31], A[31], B[31]);


endmodule

and my 32bit adder

module ripple_carry
(
  input [31:0] A, //input A
  input [31:0] B, //input B
  input cin,
  output wire [31:0] sum //Output (the sum)
);

//wire [32:0] carryout; //Carry Out from the full adder
wire cout;


//Begin adding, ripple carry style

add16b adder1(A[15:0], B[15:0], cin, sum[15:0], cout);
add16b adder2(A[31:16], B[31:16], cout, sum[31:16], gnd);

//end adding the ripples and the carries 

endmodule

how do I go about parametrizing them using the "parameter" to make them variable bit width.

Because this is a class assignment, please do not go straight out and solve it for me, but any documentation or help with a similar module would be great!

Thanks,
Jeff

 

[mrflibble]

This paper has a pretty good explanation IMO. It should also give you an idea of why you'd want to get rid of that `define.