Variable bit extraction in Verilog

[jinics]

Hi,
I want to extract variable bits from an incoming data stream. I want something like this:
Method1:
parameter MAX = 16
reg [3:0] reg1;
//reg1 is assigned the value from some register
[MAX-1:0] extracted_bits = stream_data [reg1 - 1:0]

Method2:
Since verilog does no allow variables in here.
One way to do is that I use parameters instead of reg1. i.e.

parameter MAX = 16
parameter reg1 = 5;//some value
[MAX-1:0] extracted_bits = stream_data [reg1 - 1 : 0]

This second method means that every time I want to extract another bit pattern I need to synthesize the code.

Is it possible to extract variable bits as shown in method one.

I want to change the bit selection.
I want to be able to extract variable bits from each incoming chunk based on a variable in register.

Is there some core available which can perform this or can you point me to some technique to do it efficiently.

Thanks,
jinics

 

[RBB]

You can use a case statement or a for loop. I didn't verify this code, so it may not work exactly, but should give you an idea of how to implement what you're trying to do.

`timescale 1ns/10ps

module foo(dataIn,
           dataOut,
           index);

   parameter            size = 16;

   input [size-1:0]     dataIn;
   output [size-1:0]    dataOut;
   input [3:0]          index;

   reg [size-1:0]       dataOut;
   integer              i;

   always @ (dataIn or index)
     begin
        case(index)
          4'b0000: dataOut = {{size-1{1'b0}},  dataIn[0:0]};
          4'b0001: dataOut = {{size-2{1'b0}},  dataIn[1:0]};
          4'b0010: dataOut = {{size-3{1'b0}},  dataIn[2:0]};
          4'b0011: dataOut = {{size-4{1'b0}},  dataIn[3:0]};
          4'b0100: dataOut = {{size-5{1'b0}},  dataIn[4:0]};
          4'b0101: dataOut = {{size-6{1'b0}},  dataIn[5:0]};
          4'b0110: dataOut = {{size-7{1'b0}},  dataIn[6:0]};
          4'b0111: dataOut = {{size-8{1'b0}},  dataIn[7:0]};
          4'b1000: dataOut = {{size-9{1'b0}},  dataIn[8:0]};
          4'b1001: dataOut = {{size-10{1'b0}}, dataIn[9:0]};
          4'b1010: dataOut = {{size-11{1'b0}}, dataIn[10:0]};
          4'b1011: dataOut = {{size-12{1'b0}}, dataIn[11:0]};
          4'b1100: dataOut = {{size-13{1'b0}}, dataIn[12:0]};
          4'b1101: dataOut = {{size-14{1'b0}}, dataIn[13:0]};
          4'b1110: dataOut = {{size-15{1'b0}}, dataIn[14:0]};
          4'b1111: dataOut = {{size-16{1'b0}}, dataIn[15:0]};
        endcase
     end // always @ (dataIn or index)

   always @ (dataIn or index)
     begin
        for(i = 0;  i <= index; i = i + 1)
          dataOut[i] = dataIn[i];
        for(i = index+1;  i < size; i = i + 1)
          dataOut[i] = 1'b0;
     end
endmodule