Validation Vs Verification

[uditkumar1983]

Hi all,
I am confused between verification and validation, I readed in few paper that validation is nothing but it is used to increase your confidence level exp - as doing simulation, So if doing simulation is a type of validation , then what is verification ??

Please Suggest me difference between them , and differents technique for doing it.

Please reply me ...
Thanks in Advance ..

Regards

 

[uditkumar1983]

Hi all,

Please give me your suggestion.

Thanks

 

[rsrinivas]

verification is verifying ur code for any bugs tat may be present.u write testcases to cover ur RTL for all possible cases(literally not possible) and say tat u have verified ur code if u find no bugs.
validation is verifying ur code in silicon.it is mostly a pld like fpga or cpld.

 

[raja1982y]

verification is convergence of intention, specification and implementation. This means verification is task of verifying whether the intended behaviour is captured in specification and the features captured in the specification are implemented in RTL or not.the intended behaviour.

validation is checking whether the behaviour implemented is as per speicification or not.

-Rj

 

[pintuinvlsi]

Verification is done on RTL and it has to be done before sending your chip to fab to verify that there is no functional bug or undesired behaviour is not there in the RTL.

Validation is done on real Silicon to see there is no flaw in the chip, it may be functional, memory fault or interface of the chip. This is done by putting your chip in validation board with other setup.

Hope this helps,

 

[uditkumar1983]

Hi ..
Thanks of all of you..
So Hw/Sw co simulation (On simulator) we can tell as coverification , and suppose I downloaded HW Part into FPGA/CPLD and created all real envirnment than analysis of HW-SW combinedly we can tell as HW/SW validation ????
Please comment on this ......

If any One of you having any Document related with validation Please Download it ....

Thanks in Advance ..
Regards

 

[verilog_always]

Verification is running ur design on Simulation tools and validation is running ur design in real time scenario eg on FPGA's

 

[barkha]

'Validation ensures it is the right design, verification ensures the design is right'

Verification - Done throughout design phase, basically until chip is ready to be fabricated. Debug will involve going through code or waveforms from simulations.

Validation - The testing you do in the lab once you get your chip fabricated. Debug has to be done with different instruments or software.

Verification is the act of testing a design against its specifications. Validation tests the system against its operational goals.