port map
(
x => '1',
a => (b when (x='0') else c),
y => x"0"
);
Error (10500): VHDL syntax error at test.vhd(1710) near text "WHEN"; expecting ")", or ","
my_signal <= <<whatever you want to do>>;
a => my_signal;
with x select out <= b when '0', c when others;
, it sends me an error telling that the portmapped signal should be an FPGA input signal.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 signal a : std_logic; port map ( x => '1', a => a, y => x"0" ); a <= b when (x='0') else c; -- this assumes x is declared locally
There are several problems here: First of all, you cannot do complex assignments in a port map. For '93 you cannot call functions in a port map, but in VHDL 2008 you can.
You cannot use when because "when" is not a function, and doesnt return anything, its a built in operator that works with the assignment operator (again, assignment is not a function). You will need a temporary signal.
Another confusing aspect, when cannot be used inside a process in '93 as it's meant for constant assignments, but in '08 you can (along with with/select).
Also, I not you're using x in the when assignment. This will have to be X defined in the architecture, NOT the X from the port map (as you have no visibility of these names).
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 signal a : std_logic; port map ( x => '1', a => a, y => x"0" ); a <= b when (x='0') else c; -- this assumes x is declared locally
In other words you are trying to feed a dedicated hardware input (e.g. a transmitter clock or data input) from FPGA fabric. Unless you find specific features allowing this connection, It doesn't work.but since the component for which I am port mapping is a transmitter block, it sends me an error telling that the portmapped signal should be an FPGA input signal.
In other words you are trying to feed a dedicated hardware input (e.g. a transmitter clock or data input) from FPGA fabric. Unless you find specific features allowing this connection, It doesn't work.
It's a problem of FPGA properties, not a HDL problem. Review the FPGA hardware manual about possible sources for the respective signal.
What's surprising here?however surprisingly the tx input receives clock from an internally PLL generated clock.
Can you provide the actual error?
You should also look into using the clocking primitives. More complex clocking schemes can introduce setup/hold issues. For example, switching clocks can result in a glitch if one clock is high and the other is low and about to transition.
Error (10500): VHDL syntax error at test.vhd(1710) near text "WHEN"; expecting ")", or ","
the actual error like I pointed above is
This error is just a syntax error.
What FvM and vGoodTimes are talking about are more fundamental problems in your design, as you appear to be trying to mux a clock, which is not something that should be done without proper design consideration and is not something that is fixed in VHDL.
I have 2 clocks which I want to connect to tx. During the initialization I want to connect a intern PLL generated clock but later I would like to connect a external ref clock.
The question is how can I connect tx clock to any of these 2 clocks based on my pll lock status without using a third signal.
But without any useful information besides this, perhaps the problem lies in the code of the transmitter block, which might already have I/O cells instantiated in the code. Have you looked in the source code of this transmitter?..., it sends me an error telling that the portmapped signal should be an FPGA input signal. the input signal from the FPGA is to be portmapped with the transmitter clock from the transmitter block.
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?