Using Virtex-5 Libraries Guide for Schematic Designs

[lahrach]

Hi,
How to implement the folowing portion vhdl code: using Virtex-5 Libraries Guide for Schematic Designs

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if clk'event and clk='1' then

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regards

 

[TrickyDicky]

that bit of code represents the rising edge of a clock.

Basically, this is the clock input on a register.