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Using Verilog testbench in Tetramax

prokul

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Hello all

I wander if it is possible to use Verilog/VHDL testbench in Tetramax.
Or is there any way to convert Verilog testbench to a format like STIL, readable to Tetramax?
I need to do this to run fault simulation on a sequential circuit w/o scan chains.

Any help is appreciated. Thank you
 

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