Using Verilog for Logic Simulations from a Cadence Netlist

[charlie2010]

Previously I had been using IRSIM for simple logic analysis of my digital circuit netlists from Cadence schematic, now when using Verilog-XL the logic simulations indicate 'high Z' and 'X' issues. How do I use Verilog-XL to look at the simple logic of the circuit rather than some of the physical issues?

Thanks.