Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Using VCS to compile SV filel ist

Status
Not open for further replies.

meir

Junior Member level 3
Joined
Jan 16, 2013
Messages
26
Helped
5
Reputation
10
Reaction score
5
Trophy points
1,283
Activity points
1,431
I'm trying to run command: vcs -sverilog -f filelist
but I get the error : No source file given.
When I run the same command but with a file list of only verilog files
it compiles succesfully.
what am I doing wrong ?
Thanks
 

Can you show the complete command line and the error message? Does the message report a problem on the filelist or a source file included in the filelist? Are you using any environment variables in the filelist?
 
  • Like
Reactions: meir

    meir

    Points: 2
    Helpful Answer Positive Rating
try this

vcs -R -I -f filelist +v2k +systemverilogext+.sv
 
  • Like
Reactions: meir

    meir

    Points: 2
    Helpful Answer Positive Rating
I found the problem, should have read the Error message more carefully:
Error-[NSFG] No source file given
Source file is not being with compilation option '-f'.
Please check file list and note '//' is used for comment.

The problem was that in the full path I had '//': /dir1/dir2//dir3/file.sv.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top