OK, so I select the memory controller from the IP catalog which opened a Qsys like window rather than a megawizard type window like we used to get when we select PLL and memory blocks. Why is that?
Now I select the parameters and then click generate HDL which asks me about synthesis files and simulation files. I select VHDL in both. Now I get a raft of files created in folder named simulation and another folder named synthesis. I am not sure what to do next.
There are VHD files with same name as I specified for my memory controller when I chose it, when I open them they just seem to internally instantiate the memory controller and connect it to the top level. However, there is no library file or otherwise at that explains where the memory controller itself is defined. If I try to carry out simulation in ModelSim it says that the component "is not bound". In Quartus however, it is able to figure out where the files are due to some .qip file which is a tcl script with a lot of lines, also found inside the synthesis folder.
Usually with a memory block IP, we get a megawizard window in which we click next and next until it reaches the end. There is no "Generate HDL" for it. The same is true for PLL. There we have a very clear distinct obvious manifest HDL file that we can compile and instantiate in our design top level to include that PLL or memory block into the design. However, with this specific case of memory controller it is creating a lot of files and it is not clear why, and how to get what I want.