Using PrimeTime to find net delays

[kbarber]

Hello,

I'm wanting to use Primetime as a means to find the delay of each net in my gate-level design.

When I issue the report_timing command all I receive is the following error message:

No constrained paths.

I have constrained the clock with the following command:

create_clock -period 10 [get_ports CLK]

I was under the impression that any other constraints were optional?

I've also tried using the report_timing command in Design Compiler. With DC, I at least receive some output - but each net delay is shown as 0.

Below is an example:

Point                        Fanout       Cap      Incr       Path
  ---------------------------------------------------------------------
  input external delay                               0.00       0.00 r
  key0[2] (in)                                       0.00       0.00 r
  key0[2] (net)                  1         1.92      0.00       0.00 r
  U131/ZN (INVX0)<-                                  0.06       0.06 f
  n4 (net)                       2         5.42      0.00       0.06 f
  U24/Q (OR2X1)                                      0.12       0.18 f
  n13 (net)                      1         2.59      0.00       0.18 f
  U129/QN (NAND2X1)                                  0.11       0.29 r
  t[2] (net)                     8        20.34      0.00       0.29 r
  U122/ZN (INVX0)                                    0.19       0.49 f
  sbox1_inst/n7 (net)           12        31.53      0.00       0.49 f
  U83/QN (NOR2X0)                                    0.20       0.69 r
  sbox1_inst/n14 (net)           4        10.45      0.00       0.69 r

n4 has no delay - and neither does any other net - only the fan-out is shown.

Any insight as to why PrimeTime is unable to give any reports (is it mandatory to specify more constrains than just the clock?) or how to report the delay for each individual net in DC (or PT, for that mater) would be greatly appreciated!

Thanks in advance.

-k

 

[soloktanjung]

You can use "report_timing -net" command in PT.

Thanks.

 

[oratie]

Regarding "No constrained paths." - check, that the port CLK in connected to any register in the RTL and in the synthesized netlist.

Regarding zero net delay - seems, you have not any RC values loaded (they may come from WireLoadModel or from real extraction of routed nets).

 

[kbarber]

Regarding "No constrained paths." - check, that the port CLK in connected to any register in the RTL and in the synthesized netlist.

Regarding zero net delay - seems, you have not any RC values loaded (they may come from WireLoadModel or from real extraction of routed nets).

How can you instruct the tool to use the wire load models? The tool is automatically set to select an appropriate load model - I thought that it would apply these values by default?

I've also verified that the CLK signal is indeed feeding 4 registers.

 

[soloktanjung]

Why not just put some IO constraints to your design and see if the PT will report the timing or not and then conclude that.

Regarding zero net delay, I think if you want to know the net delay in DC, it is not very accurate and not useful. There is a command in DC to set the wireloadmodel, please check the user guide as I do not remember the exact command.

Thanks.