Using Primetime(pt) to do presimulation after DC and postsimulation with sdf

[realtek]

I am a new guy in digital circuit design
Now I need use primetime(pt) to do presimafter DC) and postsim(with sdf)

Q1: I there any complete example (procedure) to learn how to write pt script , I read SOLD turtorial , but it use command like this
compile_stamp -model_file Y.mod -data_file Y.data -output Y
where Y.mod Y.data (Y.db .......) still is a blackbox for me, after following the turtorial , I still cannot understand what kind files I need to do my presim(after dc) STA.

Q2: after read some SOLD, I write a simple scrile
/**************************/
set search_path "."
set active_design MY_TOP
set currt_design {"MY_TOP"}
set clock CLK
read_verilog $active_design.v
read_db typical.db // library
read_db wireload.db //wireload model
current_design $active_design
create_clock -period 20 -waveform {0 10} $clock
set_clock_latency 2.5 [get_clocks $clock]
set_clock_transition 0.2 [get_clocks $clock]
set_clock_uncertainty 1.5 -setup [get_clocks $clock]
check_timing
report_timing


/******************************/
why the path item in report_timing is all 0, what's wrong with this script?

Q3 : If ther are many warning " Creating blackbox for ...."
How to eliminate these warning,can pt accept
//synopsys translate_off......
/**************************************/
beg for help
Tks in advance!!

 

[heartfree]

Re: primetime primer!

Did you set link_path and operating condition?

 

[realtek]

Re: primetime primer!

What Kind operation condition I need?
If I only set_clock ,can I get any path delay report ??

what does link path mean ??
my_design.v use typical.db
I use read_db to read typical.db
It's not enough??
What kind link_path I need?

 

[heartfree]

Re: primetime primer!

1.link_path specifies a list of libraries, design files, and library files used
during linking. The link_design command looks at those files and tries to
resolve references in the order of specified files.
2. operating condition spefifies PT analyze type BC or WC.
Thanks.

 

[visualart]

primetime primer!

It is the best that anyone can provide a general script on the STA.Tia

 

[liu_uestc]

primetime primer!

yes i agree

 

[rascal1125]

Re: primetime primer!

I am a new guy in digital circuit design
Now I need use primetime(pt) to do presimafter DC) and postsim(with sdf)

Q1: I there any complete example (procedure) to learn how to write pt script , I read SOLD turtorial , but it use command like this
compile_stamp -model_file Y.mod -data_file Y.data -output Y
where Y.mod Y.data (Y.db .......) still is a blackbox for me, after following the turtorial , I still cannot understand what kind files I need to do my presim(after dc) STA.

Q2: after read some SOLD, I write a simple scrile
/**************************/
set search_path "."
set active_design MY_TOP
set currt_design {"MY_TOP"}
set clock CLK
read_verilog $active_design.v
read_db typical.db // library
read_db wireload.db //wireload model
current_design $active_design
create_clock -period 20 -waveform {0 10} $clock
set_clock_latency 2.5 [get_clocks $clock]
set_clock_transition 0.2 [get_clocks $clock]
set_clock_uncertainty 1.5 -setup [get_clocks $clock]
check_timing
report_timing


/******************************/
why the path item in report_timing is all 0, what's wrong with this script?

Q3 : If ther are many warning " Creating blackbox for ...."
How to eliminate these warning,can pt accept
//synopsys translate_off......
/**************************************/
beg for help
Tks in advance!!

in Q1, 'compile_stamp_model' you used in DC it to model a timing delay between design blocks. Of course, since it is a sort of timing model, it can be used in timing analysis. Basically, after synthesis, you will generate a new netlist, SDC, and SDF .... To do STA, you only need to take your netlist, library(db), and SDC and read back to PT, then you can do repor timing.

in Q2, you may check on you log to see if any '0' occured in command parsing.
Also, in traditioal STA process, design is netlist ready. And check if 'clock' is created correctly.

in Q3, the warning may mean some modules or instances can not be mapped from library or other modules, so tool will treat it as blackbox. Still, the compilier directives is for synthesis. Since PT takes netlist to do STA, it is no reasons to let PT read such directives.

Only one tip to do STA, preparing you data as below:
* design : netlist
* timing model: library, SDF, QTM, STAMP ... etc (depends on your needs)
* constraints: SDC

Regards;