Using Multiple Processes In VHDL

[jerryt]

I have another easy question: If I use the same signal in multiple processes in a behavioral architecture using VHDL how do I know which process will run first? Is it top-down meaning the first process run into in code and then the next process in code, etc?

For example (from top down of how the code is written):

process (clk,A)
[sequential statements]
end process;

process (clk, A, reset,)
[sequential statements]
end process;

Which process will run first? Do I have to worry about the dependencies of signal A since it is in two different processes? Also, can I use port signals and declared signals in the sensitivity list for a process?

Thanks!

 

[permute]

It is an event based system. The key is the "nonblocking" assignments.

in this case, you have clk'event. this flags both processes for evaluation. nonblocking assignments within each process are evaluated, but the results are not assigned to the signals at this time. After all processes for clk'event have been evaluated, all assignments are made. Each assignment triggers a 'event for that signal -- any combinatorial process is now updated.

for this reason, a sequential process will typically only need clk and reset. otherwise A'event will cause the process to be evaluated needlessly -- neither the reset nor clock edge cases will be true, so no actual code will be reached on that evaluation.

Shared variables use blocking assignments. as such they are only used in very few use-cases in VHDL.

 

[TrickyDicky]

signals work on a scheduling system. They do no get updated until the process they are updated in suspends or waits. I am a bit worried you ask about multiple processes, because a signal can only be updated in a single process. You cannot assign a signal in multiple processes or it counts as a multple driver error (or in the case of a std_logic, you will get 'X').

Anyway, back to the scheduling thing, because of this, you can write code like this:

process(clk)
begin
  if rising_edge(clk) then
    a <= 1;
    a <= 2;
    a <= 3;
  end if;
end process;

Because the signal takes the last assignment, another process can read "a" at the next clock edge (or delta) and would read 3, because the 1 and 2 assignments got overwritten by the 3rd one.

On to your questions:
Which process will run first? Neither. They both run at the same time.
Do I have to worry about the dependencies of signal A since it is in two different processes? No, because you can only update it in a single process.
can I use port signals and declared signals in the sensitivity list for a process? Yes. But with a clocked process, you only need clock in a sensitivity list (which is probably a port) and reset if you want async reset. A port is a signal.

Permute mentions shared variables that do allow writes from multiple processes, and when they get updated will depend on the behaviour of your simulator (or carefully constructed code). I would not recommend using them though. A synthesisor will treat them as a signal during compillation (and you'll get the same multiple driver errors)

 

[jerryt]

Thanks to everyone for their responses.

TrickyDicky: You say "You cannot assign a signal in multiple processes or it counts as a multple driver error (or in the case of a std_logic, you will get 'X'). " Just to be clear for sure, do you mean that I cannot use the same signal in multiple processes sensitivity lists.

For example if I had:

process (A,B,C, clk)
....
end process;

process (B, reset)
....

Are you saying that I could not use "B" in more than one process because I would get an error when trying to synthesize?

Thanks!

 

[alexan_e]

If this was a problem then you wouldn't be able to use the clock in more than one processes...
There in no problem to read but you can only write a value from one process.

You may be interested in https://www.edaboard.com/threads/195444/
it is a way to set/clear a flag from different processes or clock domains

Alex

 

[jerryt]

Thanks Alexan. So what you are saying is that in the code below I could not write to B in both processes and it would cause an error. I can only write to B in only "1 process". Is that correct?

process (A,B,C, clk)

B <= tempB

end process;

process (B, reset)

B <= A xor C

end process;
------------------------------------

 

[alexan_e]

Yes, this can't be done because you are using hardware description language, it represents a real circuit so you can't control one electrical signal output from two different drivers.

Alex

 

[TrickyDicky]

Alexan told you the hardware answer, but in VHDL the code you posted is illegal (ie. you'll get a syntax error) unless B is a resolved type (like std_logic). This allows drivers from multiple processes, but with std_logic doing this will almost always result in B being 'X' (unknown) when you simulate, and when you try to compile it you'll just get a multiple driver error.

The only time from a hardware perspective you can drive 1 signal from multiple places is via tri-state buffers (and their RTL descriptions)

 

[jerryt]

Both great answers - I appreciate it.

Tricky - What if I use a signal assignment that is not part of the port assignment of the entity?

For example, in the code below I use a signal assignment "temp C" outside of the port assignment. In the first process I set tempC = B. In the second process I use tempC as my sensitive signal to begin running the 2nd process. Is this legal in VHDL code?

Thanks!

entity example
port (A, B, C, clk : in std_logic
Z : out std_logic);
end example;

begin

architecture behav of example

signal tempA, tempB, tempC

process (A,B,C, clk)
begin

tempB <= A
tempC <= B

end process;

process (tempC)

B <= A xor C

end process;

 

[alexan_e]

Yes you can use that, write the signal in one process and trigger another process with an event on that signal.

Alex

 

[jerryt]

Alex: However, we cannot write to a port signal in one process and trigger another process with an event on this port signal. Is that correct? I appreciate your help, thanks!

 

[alexan_e]

I'm not sure about that but I think if the port is a buffer or inout so that you are able to read the value then it could trigger another process.
I have never used anything similar.

Alex

Edit . it obviously can't be a buffer since you are asking for an output so ignore the buffer part

Edit 2 : I have no idea why I said that buffer is not an output, it is an output that can be read.
I have seen some recommendations to avoid it, it can be replaced with a signal that drives the output, when you want to read the output value you just read the signal.
VHDL coding tips and tricks: How to stop using "buffer" ports in VHDL?

 

[ozzyv]

I have a similar problem. a vending machine controller takes coins and changes states with clk. however when the coin stuck at the machine, it should not be regarded as infinite coins so i need to prevent state change in that case. Here is my code :

		Process(rst,clk)
		Begin
			if(rst='1') Then
				present_state <= st0;
			elsif( rising_edge(clk) ) then
				present_state <= next_state;
			end if;
		end process;
		
		Process(present_state,coin5_in,coin10_in,coin25_in)
		Begin
		if
			Case present_state IS
				When st0 =>
					coke_out <= '0';
					coin5_out <= '0';
					coin10_out <= '0';
					cstate <= "0000";
					
					if(coin5_in) then next_state <= st5;
					elsif(coin10_in) then next_state <= st10;
					elsif(coin25_in) then next_state <= st25;
					else next_state <= st0;
					end if;

if i used coin_valid signal(boolean) for both process, it is the same error