using multibit Flip-Flop in gate-level optimization with Design Compiler

[CCU_HRS]

Hii,
I'm remapping the gate-level netlist using design compiler and I want get new gate-level netlist which include mutlibit cell.

My original gate-level netlist have many 1 bit FF , and my new cell library have 2bit FF better than two 1bit FF
, I want mapping them with multibit FF, how can I use DC to accomplish it.

the command set hdlin_infer_multibit "default_all" just available in RTL to gate-level ,
and set_multibit_option is no change to my new netlist.

EX.
GTECH_FD1 fetch_data_if_d_reg_31 ( .D(n390), .CP(core_clk), .Q(
icache_fetch_data_if_d[31]), .QN(n75) );
GTECH_FD1 fetch_data_if_d_reg_30 ( .D(n389), .CP(core_clk), .Q(
icache_fetch_data_if_d[30]), .QN(n74) );
GTECH_FD1 fetch_data_if_d_reg_29 ( .D(n388), .CP(core_clk), .Q(
icache_fetch_data_if_d[29]), .QN(n73) );
GTECH_FD1 fetch_data_if_d_reg_28 ( .D(n387), .CP(core_clk), .Q(
icache_fetch_data_if_d[28]), .QN(n72) );

and translate them to new gate-level netlist with multibit

Best Regards

 

[yx.yang]

How about try to re-synthesis the RTL again, using your new library? Not from the Getch.

 

[CCU_HRS]

but the company give me gate-level netlist only