hello
can anyone give me a hand about using modelsim with tsmc 0.18u library?
I wanna use modelsim as my verilog code simulator and I wanna have timing analysis of my code in modelsim with tsmc 0.18u.
if it is possible can anyone tell me how?
and send me the essential files.
I know Its not the best way but It can be useful to know the timing analysis approximately during simulation before synthesis.
I have a pdf file that describes the area and delay of all gates in tsmc 0.18 u technology file but I wanna know that does any library file available for it to use it in modelsim?
for example for and 2 :
I know Its not the best way but It can be useful to know the timing analysis approximately during simulation before synthesis.
I have a pdf file that describes the area and delay of all gates in tsmc 0.18 u technology file but I wanna know that does any library file available for it to use it in modelsim?
So you are telling us that you intend to do you entire design using gates from the library instead of behavioral RTL code?
1. HDLs using Verilog, VHDL, Catapult C, etc are used to create behavioral descriptions.
2. Behavioral descriptions are synthesized into library primitives by the synthesis tool using timing constraints.
3. Now you have a gate level description where you could use the gate level simulation models from your vendor to do grossly inaccurate timing simulations.
4. Gate level simulation is slow.