using MIG for SDRAM DDR (DDR3)

[syedshan]

Dear all,

I have to implement Memory controller for DDR3 memory for my project. I am using Xilinx FPGA (virtex 6 and ISE for synthesis and implementation)

now while I was studying and discussing with one or two guys they said that using it with microblaze will be easier.
And if I use sole MIG cntroller with my design I have to face many difficulties and have to restructure my whole design.

For now I used simple dual port RAM for my design since I am little new to FPGAs and when I started I did not knew about the DDR3 RAM is so
much different than simple dual port RAM... Now sice my simulation works fine with DUAL port and my final design is to be implemented using DDR3 memory
I am in real fuss seeing all these signals and strobes since I have to deliver the product by end of of 3rd week of June and time is much less for me to start reading
and understanding the DDR3 or MIG completely...

Well definitely by hook or by crook I have to do it any ways but any guidance in this regard would be really helpful.

What to do... Please do reply....

 

[milind.a.kulkarni]

Hiii....

May I know which ISE version you are using.....However .... I used ISE 10.1 ....where I used MIG to generate the PIN outs for DDR2 not DDR3....

Now coming back to your question....

When ever you want to chose a DDR2 or DDR3 interfacing with FPGA....you need to first generate the PIN out using MIG then only you can design the boad for that interface....

After this you will get the MIG either VHDL or Verilog memory interface routing with sample test application...

One need to test the DDR mounted on the board using this interface.....

I hope this helps....

Good Luck....

 

[permute]

MIG has several options and can be very annoying to use. here is the basics:
1.) the core developers assume you use IOB's for everything for some reason, so the coregen will ask for valid locations for things like ref_clk and sys_clk and "error", even though these might not be in the end design. Really, the example isn't very good for this reason.
2.) there are a lot of UCF constraints that are important. again, they write them for the example, so you'll need to modify them slightly (usually by adding * to the start of each INST/NET constraint that is wrong.)
3.) SDP is nice because you can do reads and writes independently. However, DDR3 will favor block block accesses -- writes of 1-4kB and reads of 1-4kB. This is because there can be a large turn-around if the read address and write address are done on multiple rows within the same bank. With larger block transfers, the overhead is reduced. if you are only using DDR3 for the size, and not for the bandwidth, you should be ok with random accesses.
4.) If you do have lots of random accesses, you may benefit from some form of caching system.
5.) I'm not sure EDK's MIG gives you access to the entire RAM. IIRC, they only support 32b of the 64b interface for microblaze. It's possible the native interface would work, but I'm not sure there's any advatage over just using MIG at that point.

the 3rd week of June isn't that far away. I'd definatly look for someone where you work who has gotten this to work before.

 

[syedshan]

Dear both,

Thank you for your reply.

I am using ISE 13.2 version. The system board is a pre-set board from some manufacture and ordered and it has DDR3 already present ( so I guess I only have to find some way to communicate )

I guess I'll be using DDR3 for random access since my algorithm takes data each clock cycle and then adds them and read again after certain operation. Will share details with you later for further investigation
Before that is there any tutorial for simply investigating the working of DDR3 with Virtex 6. This will save lot of my time and I may get use to DDR3 functions and operations.

I am actually working as an RA in a lab where I am the only one to work on FPGAs so have to do it with the help of guys like you. I know time is short but will try my best to complete.