Using JFETs as variable resistors

[cipi-cips]

Re: JFET

thx a lot

 

[LvW]

Re: JFET

One comment on the polarity of Q5 in the collector path:
Wouldn´t it be better to connect the source of Q5 with the supply voltage ?
In the circuit diagram as shown the gate-source voltage - and thus the resistance of Q5 - is modulated by the output signal at the collector of the BJT. This creates a relatively large non-linearity.

 

[FvM]

Re: JFET

Basically not. BF245C (as most other JFET) has a completely symmetric chip design, see a principle drawing of NH chip from an ancient Siliconix FET Data Book. You can see the fully symmetric behaviour also from the voltage/current characteristic of linearized FET resistor as shown previously.

There are effectively no even terms in circuit-nonlinearity.

 

[LvW]

Re: JFET

OK, I did not realize that you have used the linearized JFET scheme.

 

[FvM]

Re: JFET

The circuit can't work without linearization as Eugen_E demonstrated.

Please notice, that I selected a rather low supply voltage of 5 V which is a prerequisite to operate the FETs almost in resistive region. Referencing the control voltage of upper FETs to VCC has the advantage, that the bandwidth of a differential amplifier used as control voltage source in a complete circuit has no influence on signal transmission cause it carries no AC.

 

[LvW]

Re: JFET

What about the circuit arrangement in the attachement with 3 FETs without any linearization circuitry ? As I did not want to spent to much time for the circuit it is not optimized.
The BJT operates between 3 and 4 mA and the ac gain is app. 35.
Signals of some millivolts are amplified without remarkable distortions.
As I´ve mentioned already - perhaps it can serve as some kind of exercise how to use FETs and how not to use FETs.

(By the way: I don´t know how to place the circuit direct into this text, any recommendation ?)

 

[FvM]

Re: JFET

J2 and J4 are almost operating in resistive region due to low Uds, but J3 is fully saturated. The circuit can be used as an amplifier anyway.

Only graphic file formats as jpg, gif can be included in the text, no pdf.

 

[LvW]

Re: JFET

J2 and J4 are almost operating in resistive region due to low Uds, but J3 is fully saturated. The circuit can be used as an amplifier anyway.

Yes, that´s true - however it is not a problem as the task was simply to use FET´s, without the requirement to operate them all in the quasi-linear region.

 

[FvM]

Re: JFET

Very true, there are no exact specifications for the design. As a somewhat vague specification has been said, that the FET should operate as variable resistors and create a variable amplifier. For the base voltage divider, linearity and true resistive behaviour are less important, cause they only affect the bias point rather than dynamic properties. If the amplifier is required to have a larger output voltage swing, then unsufficient resistive behaviour of the collector FET will be noticeable.

 

[cipi-cips]

Re: JFET

hmm one question can you tell me what is the purpose of the +Vcc that is connected on the power supply on the upper two JFET's and why is the ground connected on the power supply on the lower two JFET's ???

 

[FvM]

JFET

I guess, you mean the control voltage sources in the suggested linearized circuit. They are basically placeholders for any controlling source used in the design. You should know best, what's the purpose of the design. A ground referred control voltage would be the general case, I think. To have the control for the highside FETs supply independant, the control voltage must be added to the supply level. In a real design, this could be achieved e. g. by a differential amp. If the supply voltage is constant, it's just an offset, of course.

 

[cipi-cips]

Re: JFET

well you helped me a lot, thx for that... now I have more question for example how did you come with voltage number for all sources I meen you put -10V, -8, -7 and -1 is tehre any formula for that because with those numbers your output signal is briliant you can see that it is amplifed signal, but when you change those numbers you get lots of strange signals, for example output signal become NONamplified,.. hmmm is that how it should be ?

and one more thing I drawed same schematic you give me in Multisim 10 and it is working but when I put it in Electronic Workbanch 5.12 It doesnt work dont know why ???

 

[FvM]

Re: JFET

There are two aspects. If you assemble the circuit with regular fixed resistors instead of FET variable resistors, it would only work as an amplifier within certain parameters. Thus the resistances respectively the FET control voltages can't be set at will.

With FETs, you have a nonlinear control voltage to resistance characteristic, and you have a nonlinear resistance behavior when the FET voltage drop exeeds some limit, even with linearisation. This makes the circuit behaviour somewhat unwieldy or mysterious. I expressed my basic doubts regarding this technique previously.

Don't know why the circuit don't work in simulation, it can be used in a real circuit for sure, however the FET cut-off voltages have a considerably variation, while in a simulation, all FETs are equipped with identical parameters. A different tool may use different standard parameters for a specific device, cause they aren't fixed in the datasheets.

 

[cipi-cips]

Re: JFET

ok now i have new task, now I need to put another amplifier in the schematic but the end of the first (output) must be input of the another amplifier, and I have done that simply copy full first schematic and put the output signal from first to the output of second amplifier, than I have connected Osciloscop so I can monitor the output signal and then everything goes wrong because output signal is same as input signal hmmm.

 

[FvM]

Re: JFET

An AC coupling is necessary when cascading common emitter amplifiers. To recall a question from the topic start: I still don't understand the circuit purpose.

 

[cipi-cips]

Re: JFET

I dont understand too but all I need to is to try create what he is asking me to do

how to create that AC coupling ?

 

[FvM]

JFET

Have a capacitor between first and second stage.

 

[cipi-cips]

Re: JFET

hmm well if you dont understand this is what I ment to say you can see on this picture





now i dont understand why in the output line signal is bad why is teh signal straight and not sine wave ?

 

[FvM]

Re: JFET

now i dont understand why in the output line signal is bad why is teh signal straight and not sine wave ?

With the given parameters, I see still a sine voltage at output, but with higher gain, nonlinear distortions can be expected.

 

[cipi-cips]

Re: JFET

hmm strange I see line i even tryed to move Time base and Division on osciloscop and still it is a line