Using generate statements inside another generate statement in Verilog

[vlsi_freak]

Hi All,

Does verilog allows to use generate statements inside another generate statement.
I have a requirement as shon below,

generate if (A >1) // A is a top level generic
generate for (i=0; i<10; i=i+1)
begin : START
logic.....
end
endgenerate
endgenerate

The above gives errors while compiling. Any other option to use generate inside another generate.

regards,
freak

 

[ljxpjpjljx]

verilog generate

which simulator you use?

 

[vlsi_freak]

generate verilog

Hi,

Basically i use VCS. But this should be synthesizable and independant of simulator.

regards,
freak