Using Generate statements in my RTL?

[bh_letters]

rtl generate statement

Hi,

Can I use generate statements in my RTL for FPGA Design. If so, are ther any changes in the FPGA Design Flow? Do the Generate statement automatically elobrate during synthesis?

Thanks

 

[Sparc]

yes, u can use generate statements in RTL for FPGA design. If some unit is being used over & over again in ur design & ur optimizing Goal is speed and u r ready to give up the Area, generate is a more compact way to write the RTL. It's just a coding style & does not effect FPGA design Flow.

 

[bibo1978]

I agree but it merely depends on the synthesis tool so if you have an old version of synthesis tool or weak version I recommend that you didn't use the generate statement, also it adds complexity to the component name in EDIF style
So actually a good coding style would require that you don't use a generate statement but I sometimes used them and it worked fine with me

 

[nashafi]

I second this lat comment. But it depends what you are actually designing. If its a DSP application like an FIR etc , it will take a lot of time to write the code and generate saves you from that at the cost of area at the least.