shsshs
Newbie level 5
hi. in my project I have to use different clock for different inputs on one signal.
for example ,
signal clk_main : std_logic ;
clk_main <= clk_1 when input= '1' else clk_2 ;
when I tested clock is working on workbench. but on fpga it doesnot work.
Also I used dcm property of pfga to select suitable clock. This time I didnt test on testbench.
I am asking you to help about how to achieve transmiting different clocks on one signal according to inputs?
for example ,
signal clk_main : std_logic ;
clk_main <= clk_1 when input= '1' else clk_2 ;
when I tested clock is working on workbench. but on fpga it doesnot work.
Also I used dcm property of pfga to select suitable clock. This time I didnt test on testbench.
I am asking you to help about how to achieve transmiting different clocks on one signal according to inputs?