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using different clocks on one fpga

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shsshs

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hi. in my project I have to use different clock for different inputs on one signal.

for example ,

signal clk_main : std_logic ;

clk_main <= clk_1 when input= '1' else clk_2 ;

when I tested clock is working on workbench. but on fpga it doesnot work.

Also I used dcm property of pfga to select suitable clock. This time I didnt test on testbench.

I am asking you to help about how to achieve transmiting different clocks on one signal according to inputs?
 

permute

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The FPGA should have a BUFGMUX. really, there should also be BUFG_CTRL.

You should make sure you have the correct timing constraints for the design. Further, one of the muxing modes will switch instantly. You must ensure setup/hold times are met for this line. IIRC, there may also be a glitchless control line. The user guide discusses the advantages of each.

What is the exact use of the DCM in the design? if the input to the DCM is changed, then the DCM needs to be reset for several cycles.
 

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I used dcm for clock frequency multiplexing. moreover under dcm I found BUFGMUX to select suitable clock. But at this point I face with problem that is test bench didnt work. problem is that clock at the output of BUFGMUX is U . I didnt find where I am wrong. no syntesizing error but test bench didnt work. what do you think about it?
 

permute

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I'm not entirely certain what you just said.

I'm guessing "frequency multiplexing" means "frequency multiplication" or "frequency synthesis".

by "test bench", I'm assuming you mean an physical prototype. Though you might be referring to a simulation.


I'm not sure where you are using the clock mux -- on the input of the DCM, or with one of the outputs. The following could be issues:

1.) BUFGMUX and BUFGMUX_CTRL are different. BUFGMUX allows for reliable, fast switching of the clocks. It requires the user meet setup/hold times for CE, otherwise there can be a glitch. BUFGMUX_CTRL allows for glitchless switching, but generally requires both clocks exist and that a couple cycles of latency can occur between clock switching.

2.) If the clock to the DCM changes, the DCM should be held in reset for several cycles, and you should wait for the "locked" signal.

3.) If the BUFGMUX is on the output of a DCM and the output of the BUFGMUX is used for the DCM feedback, you should hold the DCM in reset when it is not the source for the clock.
 

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