TuAtAu
Advanced Member level 4
Hi Guys,
Does anyone have any example code that able to let the synthesiser to synthesis the pure VHDL code into the BRAM?
I don't want to use core gen.
Does this code is the most origin? I want even more origin! only pure VHDL describe, exclude attribute~
Thanks
Does anyone have any example code that able to let the synthesiser to synthesis the pure VHDL code into the BRAM?
I don't want to use core gen.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 library IEEE; use IEEE.std_logic_1164.all; -- -- Syntax for Synopsys FPGA Express -- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on -- entity XC3S_RAMB_1_PORT is port ( DATA_IN : in std_logic_vector (35 downto 0); ADDRESS : in std_logic_vector (8 downto 0); ENABLE : in std_logic; WRITE_EN : in std_logic; SET_RESET : in std_logic; CLK : in std_logic; DATA_OUT : out std_logic_vector (35 downto 0) ); end XC3S_RAMB_1_PORT; -- architecture XC3S_RAMB_1_PORT_arch of XC3S_RAMB_1_PORT is -- -- Components Declarations: -- component BUFG port ( I : in std_logic; O : out std_logic ); end component; -- -- Syntax for Synopsys FPGA Express component RAMB16_S36 -- pragma translate_off generic ( -- "Read during Write" attribute for functional simulation WRITE_MODE : string := "READ_FIRST" ; -- WRITE_FIRST(default)/ READ_FIRST/ --NO_CHANGE -- Output value after configuration INIT : bit_vector(35 downto 0) := X"000000000"; -- Output value if SSR active SRVAL : bit_vector(35 downto 0) := X"012345678"; -- Initialize parity memory content INITP_00 : bit_vector(255 downto 0) := X"000000000000000000000000000000000000000000000000FEDCBA9876543210"; INITP_01 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; --... (snip) INITP_07 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; -- Initialize data memory content INIT_00 : bit_vector(255 downto 0) := X"000000000000000000000000000000000000000000000000FEDCBA9876543210"; INIT_01 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; --... (snip) INIT_3F : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000" ); -- pragma translate_on port ( DI : in std_logic_vector (31 downto 0); DIP : in std_logic_vector (3 downto 0); ADDR : in std_logic_vector (8 downto 0); EN : in STD_LOGIC; WE : in STD_LOGIC; SSR : in STD_LOGIC; CLK : in STD_LOGIC; DO : out std_logic_vector (31 downto 0); DOP : out std_logic_vector (3 downto 0) ); end component; -- -- Attribute Declarations: attribute WRITE_MODE : string; attribute INIT: string; attribute SRVAL: string; -- Parity memory initialization attributes attribute INITP_00: string; attribute INITP_01: string; --... (snip) attribute INITP_07: string; -- Data memory initialization attributes attribute INIT_00: string; attribute INIT_01: string; --... (snip) attribute INIT_3F: string; -- -- Attribute "Read during Write mode" = WRITE_FIRST(default)/ READ_FIRST/ --NO_CHANGE attribute WRITE_MODE of U_RAMB16_S36: label is "READ_FIRST"; attribute INIT of U_RAMB16_S36: label is "000000000"; attribute SRVAL of U_RAMB16_S36: label is "012345678"; -- -- RAMB16 memory initialization for Alliance -- Default value is "0" / Partial initialization strings are padded -- with zeros to the left attribute INITP_00 of U_RAMB16_S36: label is "000000000000000000000000000000000000000000000000FEDCBA9876543210"; attribute INITP_01 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; --... (snip) attribute INITP_07 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; -- attribute INIT_00 of U_RAMB16_S36: label is "000000000000000000000000000000000000000000000000FEDCBA9876543210"; attribute INIT_01 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; --... (snip) attribute INIT_3F of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; -- -- Signal Declarations: -- -- signal VCC : std_logic; -- signal GND : std_logic; signal CLK_BUFG: std_logic; signal INV_SET_RESET : std_logic; -- begin -- VCC <= ’1’; -- GND <= ’0’; -- -- Instantiate the clock Buffer U_BUFG: BUFG port map ( I => CLK, O => CLK_BUFG ); -- -- Use of the free inverter on SSR pin INV_SET_RESET <= NOT SET_RESET; -- Block SelectRAM Instantiation U_RAMB16_S36: RAMB16_S36 port map ( DI => DATA_IN (31 downto 0), -- insert 32 bits data-in bus (<31 downto 0>) DIP => DATA_IN (35 downto 32), -- insert 4 bits parity data-in bus (or <35 -- downto 32>) ADDR => ADDRESS (8 downto 0), -- insert 9 bits address bus EN => ENABLE, -- insert enable signal WE => WRITE_EN, -- insert write enable signal SSR => INV_SET_RESET, -- insert set/reset signal CLK => CLK_BUFG, -- insert clock signal DO => DATA_OUT (31 downto 0), -- insert 32 bits data-out bus (<31 downto 0>) DOP => DATA_OUT (35 downto 32) -- insert 4 bits parity data-out bus (or <35 -- downto 32>) ); -- end XC3S_RAMB_1_PORT_arch;
Does this code is the most origin? I want even more origin! only pure VHDL describe, exclude attribute~
Thanks
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