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Using BRAM in FPGA(Xilinx Spartan) with MOST ORIGIN VHDL

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TuAtAu

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Hi Guys,

Does anyone have any example code that able to let the synthesiser to synthesis the pure VHDL code into the BRAM?

I don't want to use core gen.

Code VHDL - [expand]
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library IEEE;
use IEEE.std_logic_1164.all;
--
-- Syntax for Synopsys FPGA Express
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity XC3S_RAMB_1_PORT is
port (
DATA_IN    : in std_logic_vector (35 downto 0);
ADDRESS    : in std_logic_vector (8 downto 0);
ENABLE     : in std_logic;
WRITE_EN   : in std_logic;
SET_RESET  : in std_logic;
CLK        : in std_logic;
DATA_OUT   : out std_logic_vector (35 downto 0)
);
end XC3S_RAMB_1_PORT;
--
architecture XC3S_RAMB_1_PORT_arch of XC3S_RAMB_1_PORT is
--
-- Components Declarations:
--
component BUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
--
-- Syntax for Synopsys FPGA Express
component RAMB16_S36
-- pragma translate_off
generic (
-- "Read during Write" attribute for functional simulation
WRITE_MODE : string := "READ_FIRST" ; -- WRITE_FIRST(default)/ READ_FIRST/
--NO_CHANGE
-- Output value after configuration
INIT : bit_vector(35 downto 0) := X"000000000";
-- Output value if SSR active
SRVAL : bit_vector(35 downto 0) := X"012345678";
-- Initialize parity memory content
INITP_00 : bit_vector(255 downto 0) :=
X"000000000000000000000000000000000000000000000000FEDCBA9876543210";
INITP_01 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
--... (snip)
INITP_07 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
-- Initialize data memory content
INIT_00 : bit_vector(255 downto 0) :=
X"000000000000000000000000000000000000000000000000FEDCBA9876543210";
INIT_01 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
--... (snip)
INIT_3F : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DI   : in std_logic_vector (31 downto 0);
DIP  : in std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
EN   : in STD_LOGIC;
WE   : in STD_LOGIC;
SSR  : in STD_LOGIC;
CLK  : in STD_LOGIC;
DO   : out std_logic_vector (31 downto 0);
DOP  : out std_logic_vector (3 downto 0)
);
end component;
--
-- Attribute Declarations:
attribute WRITE_MODE : string;
attribute INIT: string;
attribute SRVAL: string;
-- Parity memory initialization attributes
attribute INITP_00: string;
attribute INITP_01: string;
--... (snip)
attribute INITP_07: string;
-- Data memory initialization attributes
attribute INIT_00: string;
attribute INIT_01: string;
--... (snip)
attribute INIT_3F: string;
--
-- Attribute "Read during Write mode" = WRITE_FIRST(default)/ READ_FIRST/
--NO_CHANGE
attribute WRITE_MODE of U_RAMB16_S36: label is "READ_FIRST";
attribute INIT of U_RAMB16_S36: label is "000000000";
attribute SRVAL of U_RAMB16_S36: label is "012345678";
--
-- RAMB16 memory initialization for Alliance
-- Default value is "0" / Partial initialization strings are padded
-- with zeros to the left
attribute INITP_00 of U_RAMB16_S36: label is
"000000000000000000000000000000000000000000000000FEDCBA9876543210";
attribute INITP_01 of U_RAMB16_S36: label is
"0000000000000000000000000000000000000000000000000000000000000000";
--... (snip)
attribute INITP_07 of U_RAMB16_S36: label is
"0000000000000000000000000000000000000000000000000000000000000000";
--
attribute INIT_00 of U_RAMB16_S36: label is
"000000000000000000000000000000000000000000000000FEDCBA9876543210";
attribute INIT_01 of U_RAMB16_S36: label is
"0000000000000000000000000000000000000000000000000000000000000000";
--... (snip)
attribute INIT_3F of U_RAMB16_S36: label is
"0000000000000000000000000000000000000000000000000000000000000000";
--
-- Signal Declarations:
--
-- signal VCC : std_logic;
-- signal GND : std_logic;
signal CLK_BUFG: std_logic;
signal INV_SET_RESET : std_logic;
--
begin
-- VCC <= ’1’;
-- GND <= ’0’;
--
-- Instantiate the clock Buffer
U_BUFG: BUFG
port map (
I => CLK,
O => CLK_BUFG
);
--
-- Use of the free inverter on SSR pin
INV_SET_RESET <= NOT SET_RESET;
-- Block SelectRAM Instantiation
U_RAMB16_S36: RAMB16_S36
port map (
DI   =>  DATA_IN (31 downto 0),  -- insert 32 bits data-in bus (<31 downto 0>)
DIP  =>  DATA_IN (35 downto 32), -- insert 4 bits parity data-in bus (or <35
--   downto 32>)
ADDR =>  ADDRESS (8 downto 0),   -- insert 9 bits address bus
EN   =>  ENABLE,  -- insert enable signal
WE   =>  WRITE_EN, -- insert write enable signal
SSR  =>  INV_SET_RESET, -- insert set/reset signal
CLK  =>  CLK_BUFG, -- insert clock signal
DO   =>  DATA_OUT (31 downto 0), -- insert 32 bits data-out bus (<31 downto 0>)
DOP  =>  DATA_OUT (35 downto 32) -- insert 4 bits parity data-out bus (or <35 
--   downto 32>)
);
--
end XC3S_RAMB_1_PORT_arch;



Does this code is the most origin? I want even more origin! only pure VHDL describe, exclude attribute~

Thanks
 
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gongdori

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You can find an example in ISE under template. You will see something like:


Code VHDL - [expand]
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process (<clockA>)
begin
   if (<clockA>'event and <clockA> = '1') then
      if (<enableA> = '1') then
         if (<write_enableA> = '1') then
            <ram_name>(conv_integer(<addressA>)) := <input_dataA>;
         end if;
         <ram_outputA> <= <ram_name>(conv_integer(<addressA>));
      end if;
   end if;
end process;
 
process (<clockB>)
begin
   if (<clockB>'event and <clockB> = '1') then
      if (<enableB> = '1') then
         if (<write_enableB> = '1') then
            <ram_name>(conv_integer(<addressB>)) := <input_dataB>;
         end if;
         <ram_outputB> <= <ram_name>(conv_integer(<addressB>));
      end if;
   end if;
end process;





Also, if you want to instantiate a BRAM primitive of the device you selected, you can find it on user's guide. It talks about what primitive to use, how to initialize, etc.

Gongdori
 
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TuAtAu

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Hi Gongdori,
...
<ram_name>(conv_integer(<addressA>)) := <input_dataA>;
...
..
<ram_outputB> <= <ram_name>(conv_integer(<addressA>));
...

Its an array~
r u sure arrays in a VHDL code are put into BRAM by default?

PS: the #1 post is from the user's guide template. I am not sure it is the origin VHDL? but i saw it call a library and using a predefined RAM module. I want to instantiate myself with only VHDL code.
 

gongdori

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Yes. It is an array which is accessed by two ports. Synthesizer should interpret it as a dual port memory.

I've done both ways and they worked.
If you want to target one specific device, I recommend to use the primitive from user's guide because it tells the tool what primitive to use. However, if you need to write a generic BRAM, behavioral model would be better.
 

    TuAtAu

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    thanks for helps in BRAM!

TuAtAu

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OK! got it! tried in simulation and implementation!

Code:
for array of type BYTE_RAM_TYPE is array (0 to 2047) of std_logic_vector(31 downto 0);
(summary)
Number of RAMB16BWERs used:4 available:126 3%

Thanks Gongdori!
 

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