When you generate IP, it will give you access to that specific IP and all of the ports available. If you wanted, you can just tie the address/data bits low so they dont do anything. This is what would happen if you used an inefficient infered BRAM.
Infered BRAMs are generally prefered, especially in Xilinx, as it is far more portable than the generated IP. Altera doesnt have so much of an issue because while you can generate IPs, altera gives the user control of a library of "megafunctions" that can be instantiated and constrained within the HDL code, as well as infered IP.
Device macros would be an IP block that doesnt map directly to a single base primitive. eg. a ram from the IP generator that required several BRAMs and some logic to meet the user required size.
A primitive would be individual registers, BRAMs, DSPs etc.