J90
Junior Member level 1
Hi there,
I have a project that involves a state machine. Some states require the machine to wait for a certain amount of time.
I thought of implementing the delays using some simple counters, so the design would be something like:
But wait, this way I'm gonna get some really bad glitches, ain't I?
The state machine, in order to jump to the next state, checks the value of the counter, but the counter increments its value at the same time, resulting in unpredictable results.
I thought of using something like this instead:
This way the check is being done on the rising edge of the clock, while the counter is incrementing its value on the falling edge of the same clock, resulting in no glitches.
Now, my question is, how is this going to be synthesized on the FPGA? By the way I'm working with a Spartan3 device.
Furthermore, is this going to reduce the maximum admissible clk frequency?
Thanks :wink:
I have a project that involves a state machine. Some states require the machine to wait for a certain amount of time.
I thought of implementing the delays using some simple counters, so the design would be something like:
Code:
process(clk)
begin
if rising_edge(clk) then
-- description of the state machine
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
-- description of one counter
end if;
end process;
But wait, this way I'm gonna get some really bad glitches, ain't I?
The state machine, in order to jump to the next state, checks the value of the counter, but the counter increments its value at the same time, resulting in unpredictable results.
I thought of using something like this instead:
Code:
process(clk)
begin
if rising_edge(clk) then
-- description of the state machine
end if;
end process;
process(clk)
begin
if falling_edge(clk) then
-- description of one counter
end if;
end process;
This way the check is being done on the rising edge of the clock, while the counter is incrementing its value on the falling edge of the same clock, resulting in no glitches.
Now, my question is, how is this going to be synthesized on the FPGA? By the way I'm working with a Spartan3 device.
Furthermore, is this going to reduce the maximum admissible clk frequency?
Thanks :wink:
Last edited: