I'm working in Digital signal processing with a starter kit Spartan 3e.
I would like to use the DAC and the ADC integrated in the FGPA.
I read the strater guide (ug320).
In the chapter 9 there's a timing diagram and the signal names to control the DAC.
My question is..
to use the DAC.. Do you have to create a verilog file with outputs spi_mosi, dac_sc, spi_csck and dac_clr, make the FSM to control this signals and put those outputs in the UCF and that's all? or is more complicated that i'm thinking?
the same with the amp and the ADC...
one more thing.. If someone has this files.. or an example to use one of this component could post the code please?
Hi,
First of all, it is not UG320, but UG230, and there you have the information you need, the devices are SPI based, you can find a lot of information about them online such as:
thank you for your answer....
I read the pdf file.. but I have a question..
there's a way to use the ADC or teh DAC without the picoblaze?
what about my question with the verilog file?
My question is..
to use the DAC.. Do you have to create a verilog file with outputs spi_mosi, dac_sc, spi_csck and dac_clr, make the FSM to control this signals and put those outputs in the UCF and that's all? or is more complicated that i'm thinking?
Yes of course, you need to interface those ICs through SPI interface, you need to set up some parameters and read the data. I am sure you can find a SPI controller somewhere on the net to use with these ICs.
but... is not as simple as create a .v file with the exact timing (like the figures in the ug file)? i mean.. with the input and outputs following the instructions in the pdf file..
is strictly necessary a spi controller?
i will use the dac and the adc in separated fpga's..
another question..
in the datasheet (ug230) says that the communication with the DAC is with words of 32 bits length.. that includes the don't care bits..
will I have to make this asignation to meet the requierements
sent_data = {8'bXXX, command, address, data, 4'bXXX}?
Hi, LTC2624 on spartan 3E can work in 32 byte mode and 24 , just for compatibility with soft procesors, like picoblaze. In pure verilog or vhdl you can use 24 bit, in VHDL it looks like that : dataToSend <= "00111111" & 12_bit_unsigned & "0000"; , so, from begining 0011 is command , in that case : write to and update m next 1111 is address of DACs , in that case all DACs , 12 bit data is self explanatory and 0000 are don't care bytes , if you want use 32 byte mode you just add "00000000" before command. adc\dac\amp controll is simple on this board.. in vhdl, don't know verilog ...
hi .. im too using this spartan 3e kit amp and adc...
i have configured the amp to -1 gain..... but input range im able to operate is only
around 50mVp-p... above this i get two's compliment like signal mirror imaging at higher values of the input signal... this i observe at the output of adc on chipscope .... also there is a lot of noise in the observed signal...
what are the valid i/p ranges to the pre-amp and has anybody else observed similar problem.....
hi .. im too using this spartan 3e kit amp and adc...
i have configured the amp to -1 gain..... but input range im able to operate is only
around 50mVp-p... above this i get two's compliment like signal mirror imaging at higher values of the input signal... this i observe at the output of adc on chipscope .... also there is a lot of noise in the observed signal...
what are the valid i/p ranges to the pre-amp and has anybody else observed similar problem.....
The ADC clocks out two 14 bit results over 34 clocks. I have found that the first 14 bit result is similiar to what you are getting but the second result is OK.
The chip spec says the results are 2s complement.